1. Field of the Invention
The present invention relates to a semiconductor memory device capable of reducing power consumption or to a semiconductor memory device capable of performing a high speed burn-in test.
2. Description of the Background Art
In a prior art DRAM (Dynamic Random Access Memory), a shared sense amplifier configuration is adopted in which sense amplifiers are each shared by adjacent memory cell arrays on both sides thereof as shown in FIG. 21. Referring to FIG. 21, a memory cell array MCAL includes: a plurality of memory cells MCL1 and MCL2; a bit line pair BLL and /BLL; and word lines WL0L and WL1L. The memory cells MCL1 and MCL2 are each constructed of an N channel MOS transistor 151 and a capacitor 152. The source terminal of the N channel MOS transistor 151 is connected to the bit line BLL or /BLL, the gate terminal thereof is connected to the word line WL0L or WL1L and the drain terminal is connected to one electrode of the capacitor 152. The capacitor 152 is provided between the N channel MOS transistor 151 and a terminal 153 and the other electrode (a cell plate electrode) of the capacitor 152 is connected to the terminal 153. A cell plate voltage Vcp of about half a power source voltage Vcc is supplied to the terminal 153.
When a high boosted voltage Vpp higher than the power source voltage Vcc is supplied, the word line WL0L or WL1L is activated to turn on the N channel MOS transistor 151. By doing so, one electrode of the capacitor 152 is connected to the bit line BLL or /BLL, and an electric charge is supplied to the one electrode of the capacitor 152 from the bit line BLL or /BLL to perform data write, or alternatively an electric charge flows out from the one electrode of the electrode to the bit line BLL or /BLL to perform data read. Hence, the N channel MOS transistor 151 is an access transistor for access to the capacitor 152 in performing data write or data read.
A bit line equalize circuit 160L is constructed of N channel MOS transistors 161 to 163. The N channel MOS transistors 161 and 162 are connected in series between the bit line BLL and /BLL, the N channel MOS transistor 163 is connected between the bit lines BLL and /BLL. The N channel MOS transistors 161 to 163 receive a bit line equalize signal BLEQL at each of the gate terminals thereof. When the bit line equalize signal BLEQL is activated, the N channel MOS transistors 161 to 163 are turned on and an intermediate voltage VH supplied to a node 164 between the N channel MOS transistors 161 and 162 is supplied to the bit lines BLL and /BLL to equalize the bit line pair BLL and /BLL to a prescribed voltage. In this case, the N channel MOS transistor 163 exerts a function to equalize a potential on the bit line BLL and a potential on the bit line /BLL.
N channel MOS transistors 190L and 191L are both connected between the bit line equalize circuit 160L and a sense amplifier 170 in series with the respective bit lines BLL and /BLL. The N channel MOS transistors 190L and 191L are turned on/off by a bit line select signal BLIL to connect the bit line equalize circuit 160L and the sense amplifier 170 together.
The sense amplifier 170 is constructed of P channel MOS transistors 171 to 173; and N channel MOS transistors 174 to 176. The P channel MOS transistors 172 and 173 are connected in series between the bit lines BLL and /BLL and the N channel MOS transistors 174 and 175 are also connected in series therebetween. The P channel MOS transistor 171 is connected between a power source node 177 and a node 179A and receives a sense amplifier activating signal SEP at its gate. The N channel MOS transistor 176 is connected between a node 179B and a ground node 178 and receives a sense amplifier activating signal SEN. The sense amplifier 170 differentially amplifies a potential difference between the bit lines BLL and /BLL.
An IO gate circuit 180 is constructed of N channel MOS transistors 181 and 182. The N channel MOS transistor 181 connects the bit line BLL and an input/output line IO together and the N channel MOS transistor 182 connects the bit line /BLL and an input/output line /IO together. The N channel MOS transistors 181 and 182 are turned on/off by a column select signal SCL supplied from a terminal 183.
N channel MOS transistors 190R and 191R are both connected between the bit line equalize circuit 160R and the sense amplifier 170 in series with the respective bit lines BLL and /BLL. N channel MOS transistors 190R and 191R are turned on/off by a bit line select signal BLIR to connect the bit line equalize circuit 160R and the sense amplifier 170 together.
The bit line equalize circuit 160R has the same configuration as does the bit line equalize circuit 160L and is activated/deactivated by a bit line equalize signal BLEQR.
A memory cell array MCAR includes memory cells MCR1 and MCR2, a bit line pair BLR and /BLR and word lines WLOR and WL1R. Memory cells MCR1 and MCR2 have the same configuration as do the memory cell MCL1 and MCL2.
In the configuration shown in FIG. 21, when data is inputted/outputted to/from the memory cells MCL1 and MCL2 of the memory cell array MCAL, the N channel MOS transistors 190R and 191R are turned off by the bit line select signal BLIR while the N channel MOS transistors 190L and 191L are turned on by the bit line select signal BLIL. Then, the N channel MOS transistors 181 and 182 are turned on by the activated column select signal SCL and the bit lines BLL and /BLL are connected to the respective input/output lines IO and /IO by the IO gate circuit 180. Further, the power source voltage and the ground voltage are supplied by the respective sense amplifier activating signals SEP and SEN to activate the sense amplifier 170. In a standby state, the bit line equalize signal BLEQL is activated and the bit line pair BLL and /BLL are equalized to a precharge voltage. Thereafter, when a memory cycle gets started, the bit line equalize signal BLEQL is deactivated. Subsequent to the deactivation, the word lines WL0L and WL1L are activated to input/output data to/from the memory cells MCL1 and MCL2. When data input/output finishes, the bit line equalize signal BLEQL is activated to equalize the bit line pair BLL and /BLL to the precharge potential.
Then, when data is inputted/outputted to/from the memory cells MCR1 and MCR2 of the memory cell array MCAR, the N channel MOS transistors 190L and 191L are turned off by the bit line select signal BLIL, while the N channel MOS transistors 190R and 191R are turned on by the bit line select signal BLIR. The N channel MOS transistors 181 and 182 are turned on by an activated column select signal SCL and the bit lines BLR and /BLR are connected to the respective input/output lines IO and /IO by the IO gate circuit 180. Further, the power source voltage and the ground voltage are supplied by the respective sense amplifier activating signals SEP and SEN to activate the sense amplifier 170. In the standby state, the bit line equalize signal BLEQR is activated to equalize the bit line pair BLR and /BLR to the precharge voltage. Thereafter, when a memory cycle gets started, the bit line equalize signal BLEQR is deactivated. Subsequent to this deactivation, the word lines WLOR and WL1R are activated to input/output data to/from the memory cells MCR1 and MCR2. When data input/output finishes, the bit line equalize signal BLEQR is activated to equalize the bit line pair BLR and /BLR to the precharge potential.
In such a way, in the configuration using shared sense amplifiers, data is alternately inputted/outputted to/from memory cell arrays on both sides of the sense amplifier.
In a highly integrated semiconductor memory device, a chip with a plurality of memory cells arranged in the form of a matrix thereon, all of which cells are in a normal state, is difficult to be fabricated; therefore, spare memory cells substituted for a defective memory cell are provided and when a defective cell is specified by an address, a spare memory cell is activated instead of the defective memory cell such that a perfect operation is realized. That is, a configuration is adopted in which an address of a defective memory cell is programmed in a chip in advance, an inputted address is compared with the programmed address and if coincidence arises, then a spared memory cell is activated.
Therefore, a prior art DRAM in which spare memory cells are arranged on a chip thereof has had a configuration shown in FIG. 22. That is, a memory cell array is constructed of a plurality of blocks BLK0 to BLK15 and shared sense amplifiers 170 are each inserted between adjacent blocks. Each of the plurality of blocks BLK0 to BLK15 includes: spare rows activated/deactivated by a spare row decoder 192; and regular rows activated/deactivated by a regular row decoder 193. When a defective memory cell is included in memory cells connected to a regular row, a memory cell in a spare row is activated instead of the defective row by the spare row decoder 192. In the configuration shown in FIG. 22, however, since the plurality of blocks BLK0 to BLK15 each have spare rows and regular rows, the number of spare rows increases on the chip as a whole, thereby having led to a problem of being unsuitable for high integration.
Therefore, a semiconductor memory device of a configuration as shown in FIG. 23 is disclosed in Japanese Patent Laying-Open No. 2000-67595. That is, referring to FIG. 23, of the plurality of blocks BLK0 to BLK15, the blocks BLK0 and BLK15 each include: spare rows activated/deactivated by a spare decoder 194; and regular rows activated/deactivated by a regular row decoder 195, while the blocks BLK1 to BLK14 each include only regular rows activated/deactivated by the regular row decoder 195. With such a configuration adopted, the spare rows can be concentrated in the two blocks BLK0 and BLK15, thereby enabling the number of spare rows to decreases on a chip as a whole. When each of the plurality of blocks BLK0 to BLK15 is accessed, the plurality of blocks BLK0 to BLK15 are divided into two groups and access is performed to each of the two groups. That is, as shown in FIG. 24, the two groups are formed by division as a group Gr1 including the blocks BLK0, BLK2, BLK4, BLK6, BLK8, BLK10, BLK12 and BLK14 and a group Gr2 including BLK1, BLK3, BLK5, BLK7, BLK9, BLK11, BLK13 and BLK15. Further, spare memory cells substituted for a memory cell included in the group Gr1 are disposed in the block BLK0 and spare memory cells substituted for a memory cell included in the group Gr2 are disposed in the block BLK15. When a memory cell included in the group Gr1 is defective, a spare row 230 of the block BLK0 is activated, while when a memory cell included in the group Gr2 is defective, a spare row 231 of the block BLK15 is activated.
When a defective memory cell exists in the block BLK14 included in the group Gr1 and the defective memory cell is specified by an address, however, redundancy judgment is performed on whether or not the defective memory cell is a memory cell that can be replaced with a spare memory cell included in the block BLK0. In the two blocks BLK0 and BLK14, the bit line select signal BLI is activated to connect the bit line pair and the sense amplifier together and the bit line equalize signal BLEQ is activated to equalize the bit line pair to the precharge voltage till the redundancy judgment finishes. Thereafter, the bit line select signal BLI and the bit line equalize signal BLEQ are deactivated to make preparation for activation of a word line.
When a memory cell in the block BLK0 is used instead of a memory cell in the block BLK14 as a result of redundancy judgment, it is required that the bit line select signal BLI and the bit line equalize signal BLEQ are again activated in the block BLK14. Since the blocks BLK0 and BLK14 are spaced apart from each other, a signal for deactivating the block BLK14 is delayed due to propagation delay. As a result, a time period is extended in which the bit line select signal BLI and the bit line equalize signal BLEQ are inactive; therefore, a problem has arisen since a discharge amount for deactivating the bit line select signal BLI and the bit line equalize signal BLEQ increases as shown in FIG. 25. Particularly, since the bit line select signal BLI is driven by an internal high voltage generated by a built-in pump circuit on a chip, increase in power consumption caused by increase in discharge amount is a conspicuous problem. In company with this, a necessity arises for the pump circuit of a larger capacity, having led to a problem of a larger chip area.
On the other hand, as shown in FIG. 26A, a prior art semiconductor memory device 300 includes a memory cell array divided into 4 groups Gr0 to Gr3. The groups Gr0 to Gr3 each include spare rows 301 and regular rows 302. Column redundancy judgment on a memory cell included in the groups Gr0 and Gr1 is performed by one comparison circuit and column redundancy judgment on a memory cell included in the groups Gr2 and Gr3 is performed by another comparison circuit. In order to perform a burn-in test in which a high voltage is applied at a high temperature of the order of 120xc2x0 C. in the semiconductor memory device 300, the groups Gr0 and Gr2 are simultaneously activated and the groups Gr1 and Gr3 are simultaneously activated. Therefore, a column address for specifying a column 303 is inputted and comparison can be made of the column address with a column address programmed in a redundancy circuit.
The semiconductor memory device 300, however, includes spare rows 301 in each of the groups Gr0 to Gr3; therefore, a substitution capability to substitute a spare memory cell for a defective memory cell is low in the groups Gr0 to Gr3. Hence, a semiconductor memory device 400 as shown in FIG. 26B has been proposed. The semiconductor memory device 400 includes a memory cell divided into two groups Gr0 and Gr1. Each of the groups Gr0 and Gr1 includes spare rows 401 and regular rows 402. Furthermore, column redundancy judgment on memory cells included in the groups Gr0 and Gr1 is performed by one comparison circuit. With such a configuration, the groups Gr0 and Gr1 are simultaneously activated in a burn-in test; therefore, when a column address specifying a column 403 is inputted, the column address inputted cannot be compared with a column address programmed in a redundancy circuit. That is, since the inputted column address is in common with the groups Gr0 and Gr1, no judgment can be made on whether a column address of the group Gr0 or the group Gr1 coincides with a programmed column even if the inputted column address coincides with the programmed column address. As a result, a problem has arisen since no burn-in test can be performed on a semiconductor memory device having an increased substitution capability.
It is accordingly an object of the present invention to provide a semiconductor memory device with low power consumption.
It is another object of the present invention to provide a semiconductor memory device capable of simultaneously activating a plurality of groups to perform a burn-in test.
A semiconductor memory device according to the present invention is a semiconductor memory device having a plurality of regions and each of the plurality of regions includes: a plurality of memory cell regions each including a first block including substitution rows on which first memory cells are arranged in a row direction and regular rows on which second memory cells are arranged in a row direction, and a plurality of second blocks each including regular rows without any substitution row; a plurality of redundancy circuits provided correspondingly to the respective plurality of memory cell regions and each comparing a row address of a defective memory cell with an inputted row address to output a substitution row select signal indicating the presence or absence of selection of a substitution row on the basis of a result of the comparison; a block decoder receiving the substitution row select signal to generate a block select signal for selectively activating/deactivating a first block and a plurality of second blocks included in a memory cell region corresponding to a redundancy circuit outputting the substitution row select signal received on the basis of the substitution row select signal and output the block select signal that the block decoder has generated to the first block and the plurality of second block included in the corresponding memory cell region; and a plurality of bit line equalize circuits provided correspondingly to respective plural first and second blocks included in the plurality of memory cell regions and each generating a bit line equalize signal equalizing a bit line pair included in first and second blocks, wherein the first memory cells each are a memory cell substituted for a defective memory cell among a plurality of second memory cells included in the first block and the plurality of second blocks, a plurality of second blocks in one of a plurality of memory cell regions are continuously disposed, and each of the plurality of bit line equalize circuits activates a bit line equalize signal in response to deactivation of a block select signal.
A semiconductor memory device according to the present invention includes a plurality of regions. Each of the plurality of regions includes: a plurality of memory cell regions; a plurality of redundancy circuits; a block decoder; and a plurality of a bit line equalize circuits. The plurality of memory cell regions each includes a first block and a plurality of second blocks. The plurality of second blocks are continuously disposed. The block decoder outputs a block signal for selecting a plurality of blocks to the first block and the plurality of second block included in each of a plurality of memory cell regions. Each of a plurality of bit line equalize circuits activates a bit line equalize signal in response to deactivation of the block select signal. Thereby, a plurality of second blocks receive a block select signal with reduced propagation delay. Therefore, according to the present invention, a timing of activation of an inactive bit line equalize signal can be almost the same for each of a plurality of second blocks. As a result, a discharge amount when a bit line equalize signal is deactivated is reduced, thereby enabling realization of a semiconductor memory device with low power consumption.
It is preferable that each of the plurality of memory cell regions further includes: a third block disposed between the first block and the plurality of second blocks; a plurality of sense amplifiers each selectively amplifying read data from two adjacent blocks, wherein the third block is a first or second block constituting another memory cell region.
A first block and a second block including substitution rows are simultaneously activated in one memory cell region. Therefore, according to the present invention, first and second blocks are kept active till a comparison period between a row address of a defective memory cell and an inputted row address ends and after the comparison period ends, one of the two blocks that have been activated continues to be active, thereby enabling high speed operation of a semiconductor memory device to be realized.
It is preferable that each of the plurality of redundancy circuits of the semiconductor memory device further generates a substitution row activating signal for activating/deactivating a substitution row on the basis of a result of the comparison and each of the plurality of regions further includes: a plurality of substitution row decoders provided correspondingly to the respective plurality of memory cell regions and each activating/deactivating a substitution row in response to a substitution row activating signal.
A substitution row decoder performs activation of a substitution row in response to a substitution row activating signal from a redundancy circuit. Therefore, according to the present invention, a block including substitution rows can be activated at almost the same timing that a block including no substitution row can be activated according to a block select signal with reduced propagation delay and a substitution row included in the block can also be activated.
It is preferable that a block decoder outputs a first block select signal activating a first block and a second block select signal activating one of a plurality of second blocks to each of a plurality of memory cell regions till a comparison period ends in which a row address of a defective memory cell and an inputted row address are compared with each other and after the comparison period ends, outputs a third block select signal for activating one of a first block and a plurality of second blocks to each of a plurality of memory cell regions in response to a substitution row select signal.
During a period when it is judged whether or not a memory cell specified by an inputted address is a defective memory cell, a block including the memory cell specified by an inputted address and a block including a spare memory cell substituted for the memory cell specified by an inputted address if the memory cell specified by an inputted address is a defective memory cell are simultaneously activated, and after the judgment period finishes the block including the memory cell specified by an inputted address or the block including the spare memory cell continues to be kept active. Therefore, according to the present invention, a high speed semiconductor memory device can be realized.
It is preferable that the semiconductor memory device further includes: a control circuit generating an equalize control signal for controlling equalization of a bit line pair, wherein in refresh operations of a first and second memory cells, the control circuit generates an equalize control signal for deactivating a bit line equalize signal after a comparison operation performed by a redundancy circuit ends and each of a plurality of bit line equalize circuits activates/deactivates a bit line equalize signal in response to the equalize control signal.
In the semiconductor memory device, in a refresh operation of memory cells, all the blocks included in all of a plurality of memory cell regions are deactivated till a comparison period in which a row address of a defective memory cell is compared with an inputted row address ends, and after the comparison period ends, one block is activated and data is inputted/outputted to/from memory cells. Therefore, according to the present invention, power consumption is suppressed in the comparison period, and thereby a semiconductor memory device with low power consumption can be realized.
It is preferable that the control circuit of the semiconductor memory device further generates a word line control signal for activating a word line included in first and second blocks after deactivating a bit line equalize signal.
In a refresh period of memory cells, a word line included in an activated block is activated according to a row address after a comparison operation in a redundancy circuit ends. Hence, according to the present invention, power consumption of a semiconductor memory device can be surely suppressed in a refresh period of memory cells.
It is preferable that in a refresh operation of memory cells, the control circuit continues to generate an equalize control signal at a first logical level for an entire period of a comparison operation and generates an equalize control signal at a second logical level after the comparison operation ends; and each of a plurality of bit line equalize circuits generates a bit line equalize signal at the second logical level in response to the first logical level of the equalize control signal till the comparison operation ends, while generating a bit line equalize signal at the second logical level or at the first logical level in response to the second logical level of the equalize control signal and the first or second logical level of a block select signal after the comparison period ends.
The control circuit controls such that the circuit keeps blocks inactive till the comparison operation ends by switching logical levels of an equalize control signal while activating a selected block after the comparison operation ends. Hence, according to the present invention, a control circuit controlling so as to suppress power consumption in a refresh operation can be constituted of a logic circuit.
A semiconductor memory device according to the present invention is a semiconductor memory device including a plurality of regions and each of the plurality of regions includes: a plurality of memory cell regions each including a first block including substitution rows on which first memory cells are arranged in a row direction and regular rows on which second memory cells are arranged in the row direction, and a plurality of second blocks each including regular rows without any substitution row; a plurality of row redundancy circuits provided correspondingly to the respective plurality of memory cell regions and each comparing a row address of a defective memory cell with an inputted row address to output a substitution row activating signal activating/deactivating a substitution row and a substitution row select signal indicating the presence or absence of selection of a substitution row on the basis of a result of the comparison; a block decoder receiving the substitution row select signal to generate a block select signal from the substitution row select signal for selectively activating/deactivating a first block and a plurality of second blocks included in a memory cell region corresponding to a redundancy circuit outputting the substitution row select signal received and output the block select signal to a first block and a plurality of second block included in the corresponding memory cell region; a plurality of substitution row decoders provided correspondingly to a plurality of first blocks included in a plurality of memory cell regions to each activate/deactivate a substitution row on the basis of a block select signal and a substitution row activating signal; a plurality of row decoder provided correspondingly to a plurality of second blocks included in a plurality of memory cell regions to each activate/deactivate a regular row on the basis of a block select signal and a row address signal; a column redundancy circuit comparing a column address of a defective memory cell with an inputted column address to generate a substitution column activating signal for activating/deactivating a substitution column to which a memory cell substituted for the defective memory cell is connected on the basis of a result of the comparison; a substitution column decoder activating/deactivating a substitution column on the basis of the substitution column activating signal; and a column decoder activating/deactivating a regular column on the basis of a column address, wherein the first memory cells each are a memory cell substituted for a defective memory cell among a plurality of second memory cells included in a first block and a plurality of second blocks, the column redundancy circuit includes: a storage circuit storing a column address of a defective memory cell included in a first block and a plurality of second blocks in each of a plurality of memory cell regions and selectively outputting a stored column address according to a region address specifying one of the plurality of memory cell regions; and a comparison circuit comparing a column address outputted from the storage circuit with an inputted column address to output a substitution column activating signal; in a period of a burn-in test, the block decoder receives a degenerated region address to output a block select signal for simultaneously activating a plurality of blocks specified by the same block address included in a plurality of memory cell regions; and the storage circuit selectively outputs a column address stored therein corresponding to a memory cell region specified by a region address.
In a semiconductor memory device according to the present invention, in a period of a burn-in test, word lines of the same address included in a plurality of memory cell regions are simultaneously activated while bit lines included in each of the plurality of memory cell regions are activated independently of the others. Therefore, according to the present invention, a burn-in test can be performed simultaneously over a plurality of memory cell regions. As a result, the burn-in test can be performed in a short time.
It is preferable that the storage circuit of the redundancy circuit further outputs a correspondence signal showing whether or not an outputted column address is a column address corresponding to a memory cell region specified by a region address and the comparison circuit thereof outputs a substitution column activating signal when receiving a correspondence signal showing that a column address outputted from the storage circuit is a column address corresponding to a memory cell region specified by a region address.
When an inputted column address coincides with a column address of a defective memory cell and a correspondence signal showing the column address of a defective memory cell is effective is inputted, the comparison circuit outputs a substitution column activating signal. Therefore, according to the present invention, it is prevented that a spare memory cell is activated instead of a normal memory cell.
It is preferable that the semiconductor memory device further includes: a row address buffer latching an address signal to output a row address of n (n is a natural number) bits; and a degeneration circuit outputting a degenerated signal of k bits (k is a natural number satisfying 1xe2x89xa6k less than n) by degenerating a row address of k bits included in the row address of n bits, wherein the block decoder receives the degenerated signal and a block address of m (m is a natural number satisfying 1xe2x89xa6m less than nxe2x88x92k) bits, a row decoder receives a row address of nxe2x88x92kxe2x88x92m bits from a row address buffer and the storage circuit receives a row address of k bits from the row address buffer.
In a period of a burn-in test, the block decoder receives a degenerated row address of k bits and a non-degenerated row address of m bits to simultaneously activate a plurality of blocks specified by the row address of m bits included in a plurality of memory cell regions and a row decoder activates a word line included in a block activated by the non-degenerated nxe2x88x92mxe2x88x92k bits. Therefore, by degenerating k bits of a row address of n bits, a plurality of blocks of the same address included in a plurality of memory cell regions can be simultaneously activated.
It is preferable that the comparison circuit outputs a deactivated substitution column activating signal when receiving an activated first test mode signal and further outputs a substitution column activating signal activating a substitution column specified by a column address of the substitution column when receiving an activated second test mode signal.
In a burn-in test, the first test mode signal is activated to perform a test on a memory cell connected to a regular column and thereafter, the second test mode signal is activated to perform a test on a memory cell connected to a substitution column. Therefore, according to the present invention, all the memory cells can be tested in a burn-in test.
It is preferable that the comparison circuit includes: a coincidence detecting circuit detecting whether or not a column address outputted from a storage circuit coincides with an inputted column address to output a coincidence/non-coincidence signal on the basis of a result of the detection; a first test mode circuit outputting a deactivating signal for deactivating a substitution column activating signal when receiving a activated first test mode, and outputting a coincidence/non-coincidence signal from said coincidence detecting circuit when receiving a deactivated first test mode; and a second test mode circuit outputting an activated substitution column activating signal on the basis of a column address when receiving an activated second test mode signal, and outputting a substitution column activating signal on the basis of a deactivating signal from the first test mode circuit or a coincidence/non-coincidence signal when receiving a deactivated second test mode signal.
A substitution column activating signal is activated/deactivated according to a coincidence/non-coincidence signal when deactivated first and second test mode signals are inputted. The substitution column activating signal is deactivated when activated first test mode signal and a deactivated second test mode signal are inputted. A substitution column is activated according to an inputted column address when activated first and second test mode signals are inputted. Therefore, according to the present invention, various kinds of tests can also be performed using two test mode signals.
It is preferable that the coincidence detecting circuit is constituted of a first operational circuit performing an exclusive OR operation on a column address outputted from a storage circuit and an inputted column address, the first test mode circuit is constituted of a second operational circuit performing an AND operation on an output signal from the first operational circuit and an inverted signal of a first test mode, and the second test mode circuit is constituted of a third operational circuit performing an AND operation on a column address and a second test mode signal and a fourth operational circuit performing an OR operation on an output signal from the second operational circuit and an output signal from the third operational circuit. Therefore, according to the present invention, various kinds of test modes can be realized by the logic circuits.
It is preferable that a column redundancy circuit is constituted of a plurality of redundancy circuits provided correspondingly to respective plurality of substitution columns and a prescribed number of redundancy circuit among the plurality of redundancy circuits each include a storage circuit in which a column address of a defective memory cell is at least electrically written to store the written column address therein.
A column address of a defective memory cell is electrically written in some redundancy circuits among the plurality of redundancy circuits. Therefore, according to the present invention, a column address of a defective memory cell can be written even when the defective memory cell is detected in a test after a semiconductor memory device is packaged. As a result, a fraction defective can be reduced.
It is preferable that each of the plurality of row redundancy circuits include a plurality of redundancy circuits provided correspondingly to a plurality of substitution rows and each of a prescribed number of redundancy circuits among the plurality of redundancy circuits includes a storage circuit in which a row address of a defective memory cell is at least electrically written to store the written row address therein.
A row address of a defective memory cell is electrically written in some redundancy circuits among the plurality of redundancy circuits. Therefore, according to the present invention, a defective memory cell can be functionally saved even when the defective memory cell is detected in a test after a semiconductor memory device is packaged. As a result, a fraction defective can be reduced.
It is preferable that a storage circuit includes: a first fuse circuit constituted of a first fuse to be blown by supplying a current; and a second fuse circuit constituted of a second fuse blown by irradiation with laser light, wherein a column address is written in the first fuse circuit by blowing the first fuse and the second fuse becomes conductive in the second fuse circuit to output the same logical signal as that of a column address outputted from the first fuse circuit.
By supplying a current in the first fuse circuit, the fuse is blown to write a column address of a defective memory cell. Therefore, according to the present invention, a column address of a defective memory cell can be easily written by supplying a current.
It is preferable that a first fuse is constructed of a first conductor which is blown and a second conductor disposed so as to sandwich the first conductor at least vertically or horizontally.
When a current flows through the first and second conductors, a temperature of the first conductor rises higher than that of the second conductor. Therefore, according to the present invention, the first conductor can be easily blown even with a small current.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.